I am currently working as an AI Chip Architect at FuriosaAI, where I collaborate with the Compiler and Programming Language teams on chip design. I hold an M.S. in AI Semiconductor from KAIST (CASYS Lab), specializing in HW-SW co-design for AI acceleration, and have honed my research and engineering skills across both hardware and software domains through top-tier publications and projects — gaining hands-on experience in FPGA prototyping, RISC-V architecture, and custom accelerator design.
Studied AXI protocol, interrupts, and DMA of the Cheshire RISC-V SoC. Integrated the Genesys accelerator with the Cheshire RISC-V SoC and verified functionality with QuestaSim.
Built and integrated a custom NPU with a RISC-V core to accelerate MLP tasks. Built the full system hierarchy — hardware, kernel, user function, application — and verified functionality with VCS and Verdi.
Architected a systolic-array accelerator on FPGA for image detection acceleration. Implemented a dual-mode (WS/OS) systolic-array hardware and kernels for tiled WS/OS matmul; authored the CS411 class project instructions covering FPGA, Vivado, and hardware design.