Career Profile
M.S. in AI Semiconductor from KAIST (CASYS Lab), specializing in HW-SW co-design for AI acceleration. I have honed my research and engineering skills across both hardware and software domains through top-tier publications and projects. I am now seeking an RTL development position where I can leverage my hands-on experience in FPGA prototyping, RISC-V architecture, and custom accelerator design to build real-world AI hardware solutions.
Experiences
- During collaboration from 2024 March to 2025 Aug, visit the ACT Lab under Prof. Hadi Esmaeilzadeh for 2 weeks at November.
- Actively participate in research discussion and implement several accelerator simulators and compiler.
- Research details are to be announced (TBA).
- Participate in ‘Dacapo [ISCA’24]’ paper. Architected DaCapo hardware and participated in DaCapo software simulator development.
- Led the “Systolic-Array on FPGA” project for CS411 (System for Artificial Intelligence).
- CS411(2023 FALL)
- CS230(2024 FALL)
Projects
Performance analysis infrastructure for the accelerator on SoC
- Studied AXI protocol, interrupt, DMA of Cheshire RISC-V SoC. Integrated the Genesys accelerator with the Cheshire RISC-V SoC. Checked functionality with Questasim.
End-to-End AI acceleration system
- Built and integrated custom NPU with a RISC-V core to accelerate MLP tasks. Built an entire system hierarchy: Hardware - Kernel - User function - Application. Verified functionality with VCS and Verdi.
Systolic-Array on FPGA
- Architected Systolic-Array accelerator on FPGA for image detection acceleration. Implemented a dual-mode (WS/OS) Systolic-Array hardware on FPGA and kernels for tiled-WS/OS-matmul. Made class project instructions (CS411), steps of FPGA, Vivado, Hardware design.
Publication
ISCA, 2024 [Distinguished Artifact Evaluation Awards]