Career Profile
Master’s student of CASYS Lab (KAIST)
Experiences
- During collaboration from 2024 March, visit the ACT Lab under Prof. Hadi Esmaeilzadeh for 2 weeks at November.
- Actively participate in research discussion and implement several accelerator simulators and compiler.
- Research details are to be announced (TBA).
- CS411(2023 FALL) - I organized the projects of this course from scratch. In detail, The project topic is implementing systolic-arrays with verilog on FPGA(PYNQ-Z2 board) and run end-to-end image-detection neural network using FPGA accelerator.
- CS230(2024 FALL)
- Participate in ‘Dacapo [ISCA’24]’ paper.
- In detail, I contributed to Dacapo’s hardware implementation, synthesis and hardware simulator part.
Projects
RISC-V + Accelerator Integration.
- Integrate the Cheshire RISC-V SoC from PULP group and Genesys from ACT LAB via Verilog programming. Accelerator controlled by RISC-V, upon completion of its operation, generate interrupt so that RISC-V can handle interrupt. Check it using Questasim. Keywords - AXI, RISC-V, End-to-end, MMIO
End-to-end SYSTOLIC-ARRAY over the FPGA . [Projects ( 2023.7 ~ 2023.9 )]
- Developed and implemented a systolic array on a PYNQ-Z2 FPGA board. Demonstrated the board running a real image detection model as part of a major course project (KAIST CS411). Keywords - FPGA, End-to-end accelerator, Verilog, VIVADO.
RISC-V + NPU (systolic array) for MLP task (MNIST) [2024 Spring]
- Integrated an NPU (systolic array) with a RISC-V processor via the APB communication protocol. Verified the functionality of an MLP model (using the MNIST dataset). Keywords - MMIO, ARM AHB-Lite, NPU, Systolic array. Note: This project is in the verification stage and has not been synthesized yet.
Publication
ISCA, 2024 [Distinguished Artifact Evaluation Awards]