Career Profile

Master student of CASYS Lab (KAIST)

Experiences

Undergraduate Student Research Intern

2022.6 - 2023.11
CASYS (prof. JongSe Park)
  • Participate in ‘Dacapo [ISCA’24]’ paper Hardware part mainly and SW simulator part a little.
  • Prepare CS411 project : Build end-to-end Systolic array on FPGA (PYNQ-Z2).

Co-Researcher

2024.4 - 2024.11 (visit UCSD for 2 weeks at November)
ACT Lab of UCSD (prof. Hadi Esmaeilzadeh)
  • TBA

Projects

Building end-to-end FPGA_SYSTOLIC ARRAY. [Projects ( 2023.7 ~ 2023.9 )] - Build Systolic array on FPGA Board (PYNQ-Z2) and run real image detection model on it. This project is the major part of course project of KAIST CS411 class.
RISC-V + NPU (systolic array) for MLP task (MNIST) [2024 Spring] - Attach NPU(systolic array) to RISC-V via APB communication protocol and verify functionality of MLP model (dataset: MNIST). (but not synthesized yet) [Keyword : MMIO, ARM AHB-Lite, NPU, Systolic array]

Publication

  • DaCapo: Accelerating Continuous Learning in Autonomous Systems for Video Analytics
  • Yoonsung Kim, Changhun Oh, Jinwoo Hwang, Wonung Kim, Seongryong Oh, Yubin Lee, Hardik Sharma, Amir Yazdanbakhsh, Jongse Park
    ISCA, 2024 [Distinguished Artifact Evaluation Awards]

    Skills & Proficiency

    Python, C, CUDA

    RTL Language develop (Verilog, Chisel, System Veilog)

    Digital Circuit Design tools [Questasim, Vivado, Design Compiler, VCS]